Memory cells, which are used for example in so-called DRAMs (Dynamic Random Access Memories) have a capacitor, which can store a bit by virtue of its charge. For reading and writing the information in the memory that is for introducing or interrogating a charge in the capacitor, use is made of a field-effect transistor (FET) which is connected to a word line by the gate conductor (GC) and to a bit line by a second source-drain junction. The semiconductor memory then comprises a multiplicity of these memory cells, which can then be addressed via word and bit lines.
In the constant endeavors to reduce the structure widths in order to attain an increase in the packing density in the semiconductor wafers, the intention also is to reduce the geometrical extents of memory cells. For this reason, such memory cells can be constructed vertically in a semiconductor substrate, i.e., the capacitor, in particular, can be introduced into the depth of the substrate and the FET can be constructed vertically and arranged above the capacitor.
German patent application 101 11 760.4 describes a method for fabricating a memory cell of a semiconductor memory in which a trench is etched into a substrate having a semiconductor layer. This is done in such a way that a web remains, which is surrounded by the trench. The dielectric of the capacitor is then applied on the sidewall of the web. The trench is subsequently provided with a trench filling which then serves as a common capacitor electrode of adjacent memory cells. The structure of the FET is then realized on the top side of the web.
In this method, it is necessary to use crossed lines during the lithography in order to produce the webs. This constitutes a critical process step, which can only be realized with difficulty in the case of the present-day prior art.
The depth of the trench etching is stopped by the insulation layer when using an SOI substrate (silicon on insulator material). The insulation is necessary in order to terminate the memory node at its underside. Such a substrate uses predoped wafers (n+ doped), which are usually produced by the epitaxial growth of undoped silicon on doped silicon. An entrainment of dopant into the upper layers, intended as an undoped region, is caused in the process. This will flatten the profile of the lower source-drain junction, which leads to a poor current yield of the FET. Even if the entrainment of the dopant were not taken into account, this source-drain junction is nonetheless subjected to all the heat treatment steps of the process flow, which will lead to a flattening of the profile and to further power losses.
In this known method, free-standing silicon webs are produced which, in practice, must have an aspect ratio of approximately 90 in order to obtain a capacitor with sufficient capacitance. Such a structure is mechanically unstable during wet cleaning and heat treatment processes, such as e.g., when cleaning the side areas after etching and annealing possible etching damage.
Since individual webs surrounded by the trench are formed in this method, a memory cell realized in this way initially also has no direct connection to a continuous word line of the memory. The connection between the gate and a word line is effected in a self-aligned manner with the bit line. However, in the case of lithographic superposition tolerances of typically 0.4 F, where F is the minimum feature size which can be produced lithographically, as has to be assumed in functional concepts, this can lead to short circuits between the word line and the upper source-drain junction.